Very true. The lack of implicit sequencing is the hardest thing for people to understand from an imperative programming background. You need a different set of conceptual structures such as the state machine and the pipeline. This is why the various C-to-Verilog tools remain niche, they can translate behaviour but not redesign for you.
I also agree that it's stuck in the 70s, comparable to Fortran 77 or ALGOL. Bundling related signals and functionality together to produce something corresponding to an "object" or a "type" is basically impossible. All sorts of errors that could be caught automatically or discouraged by language design aren't. There's a lot of typing, and necessary duplication of effort. IDEs don't help much.
Heavy unit and system testing is fortunately widespread. Because it's the only way to ensure you end up with something that actually works.
I have a back-burner project to design a more modern language that compiles to Verilog which would make this sort of thing much more accessible.
I also agree that it's stuck in the 70s, comparable to Fortran 77 or ALGOL. Bundling related signals and functionality together to produce something corresponding to an "object" or a "type" is basically impossible. All sorts of errors that could be caught automatically or discouraged by language design aren't. There's a lot of typing, and necessary duplication of effort. IDEs don't help much.
Heavy unit and system testing is fortunately widespread. Because it's the only way to ensure you end up with something that actually works.
I have a back-burner project to design a more modern language that compiles to Verilog which would make this sort of thing much more accessible.