Interesting, the article mentions an earlier project called debit that was removed from the web in 2010:
"The most concerted and successful published bitstream reverse-engineering effort came from a tool named debit by Note and Rannaud [10]. Debit provided substantial capabilities for Virtex2, Virtex4, Virtex5, and Spartan3, with anticipated extension to Altera architectures, but seems to have attracted too much unfavorable attention. The host site http://www.ulogic.org/trac was permanently removed from service in summer of 2010."
You can check the active project instead. For example, documenting Lattice ECP5 [1] bitstream format or Xiling 7 one [2]. Everyone can help by documenting other formats too.
"The most concerted and successful published bitstream reverse-engineering effort came from a tool named debit by Note and Rannaud [10]. Debit provided substantial capabilities for Virtex2, Virtex4, Virtex5, and Spartan3, with anticipated extension to Altera architectures, but seems to have attracted too much unfavorable attention. The host site http://www.ulogic.org/trac was permanently removed from service in summer of 2010."
http://web.archive.org/web/20100829010809/http://www.ulogic....
A more recent effort for open source bitstream generation:
https://symbiflow.github.io/