The Spartan 6 FPGA can have DRAM controllers built in as a hard block, it won't use up any FPGA gates.
The issue is that you then need to interface this to the CPU, modern DRAMs like to transfer bursts of several words and you need somewhere to put this. The obvious target is to one line in a cache but as the linked email states a cache controller for the Oberon RISC would be more complicated than the designers wanted for the project.
The issue is that you then need to interface this to the CPU, modern DRAMs like to transfer bursts of several words and you need somewhere to put this. The obvious target is to one line in a cache but as the linked email states a cache controller for the Oberon RISC would be more complicated than the designers wanted for the project.